| ??? 12/05/12 04:39 Read: times | #188966 - dV/dT etc Responding to: ???'s previous message | 
| Kai Klaas said:  ......
 During a power down, on the other hand, Vcc must fall sufficiently slowly so that the BOR can trip a reset. After each power down Vcc must fall down to 0V. I know designers in the Alarm sector, who often use power-removal-watchdogs, as this catches everything. It will recover from a latch-up, and any pgm crash that fell between two stools of POR and BOD. Quite a few parts have pins called RESET that are more correctly 'reset request' pins. | 




