stefan;
on a more serious note imagine a shifter.u load data and give clock.it starts shifting out data bit by bit and in end all
registers are filled with zero.
i quote from philips manual
" Title: more about mode1"
" as data bits are shift out to right,zeros are clocked in from left.when MSB of the data byte is at the output position 1 which was initially written into 9th position is just to left of MSB and all positions to left are zero.this flags TX control unit to do at least 1 shift and deactivate send and set TI"

have a look at diag.there seems to be a delay latch that shifts in 0 every time.

i think after shift out there should be zero in it.
comments requested.
pranav phatak