Aman:
Thank you for your explanation above, and it is what I expected too because all i/o configuration is set by the SFR port registers (P0 ~ P3 registers). Cheer.. :-)

I did read those documentation as you all mention above. Actually I'm been building up the 8051 system into FPGA core but I just reliase that P0 is seem like can't configure to output (means I can't send data to external devices) but in H-Zi instead, although the P0 latch (SFR register) is set to 0xFF (and at the same time, it configured as the input as well). Any commend on it?? Anyway, I will read those data sheet again...

Thank for your help.

Best regard,
Alex Au