Latch is needed to extract lower 8 bit address from multiplexed addr/data port i.e. P0.

You may use some chips that have built in multiplexed bus input with ALE input, but not recommended as non-std devices.

To interface a std RAM connect RD (P3.7) to OE of RAM, WR (P3.6) to WE of RAM, these are active low signals, and derive CS/CE of RAM using some address decoding technique. The simplest can be connect P2.7 to CE and access RAM for address space 0000-7FFF HEX.

HITESH.