Marcio,

I agree that reading/write to registers is a suitable test for checking the chip.

From what you have said previously your base address is C(Y*2)XXH. Where Y=reg address 0-7.

You said the Register Address lines are found upon:

P2.3=A2;
P2.2=A1;
P2.1=A0;
P2.0=X.

So your registers offset by 200H.

Base Reg+0 =11000000 xxxxxxxxB or C0XXH
Base Reg+1 =11000010 xxxxxxxxB or C2XXH
Base Reg+2 =11000100 xxxxxxxxB or C4XXH
Base Reg+3 =11000110 xxxxxxxxB or C6XXH
Base Reg+4 =11001000 xxxxxxxxB or C8XXH
Base Reg+5 =11001010 xxxxxxxxB or CAXXH
Base Reg+6 =11001100 xxxxxxxxB or CCXXH
Base Reg+7 =11001110 xxxxxxxxB or CEXXH

The min spec for the width of IOR/IOW is 150ns so you are ok there but interestingly page 76 of the SMC spec indicates a 40ns delay between nCS and IOW. Since your decode use 8051 wr & rd you are not maintaining this.

regards,
p