This is a bit obscure, but I came across some odd bits in the manuals which lead to this,

In the Intel manual the description for JBC reads
"Note: When this instruction is used to test an output pin the value used as the original data will be read from the output data latch not the input pin" (page 2-46 in my downloaded copy)

In the Dallas 80C320 manual (and I'm sure in the original Intel manual) in section 10, Parallel I/O a section detailing Read_modify_write instructions lists instructions that read the state of the port data latch (page 102 of Dallas high-speed micro controller users guide)

;A NASTY ROUTINE TO ESTABLISH THE STATE OF P2 LATCH

GETP2: MOV A,#00
JBC P2.0,SET0 ;JUMP IF BIT 0 SET
RP1: JBC P2.1,SET1 ;JUMP IF BIT 1 SET
RP2: JBC P2.2,SET2 ;JUMP IF BIT 2 SET
RP3: JBC P2.3,SET3 ;JUMP IF BIT 3 SET
RP4: JBC P2.4,SET4 ;JUMP IF BIT 4 SET
RP5: JBC P2.5,SET5 ;JUMP IF BIT 5 SET
RP6: JBC P2.6,SET6 ;JUMP IF BIT 6 SET
RP7: JBC P2.7,SET7 ;JUMP IF BIT 7 SET
RP8: RET

SET0: SETB ACC.0 ;SET BIT IN ACC
SETB P2.0 ;RESET BIT IN PORT
JMP RP1
SET1: SETB ACC.1 ;SET BIT IN ACC
SETB P2.1 ;RESET BIT IN PORT
JMP RP2
SET2: SETB ACC.2 ;SET BIT IN ACC
SETB P2.2 ;RESET BIT IN PORT
JMP RP3
SET3: SETB ACC.3 ;SET BIT IN ACC
SETB P2.3 ;RESET BIT IN PORT
JMP RP4
SET4: SETB ACC.4 ;SET BIT IN ACC
SETB P2.4 ;RESET BIT IN PORT
JMP RP5
SET5: SETB ACC.5 ;SET BIT IN ACC
SETB P2.5 ;RESET BIT IN PORT
JMP RP6
SET6: SETB ACC.6 ;SET BIT IN ACC
SETB P2.6 ;RESET BIT IN PORT
JMP RP7
SET7: SETB ACC.7 ;SET BIT IN ACC
SETB P2.7 ;RESET BIT IN PORT
JMP RP8
;I TOLD YOU IT WAS NASTY
END


The JBC instruction is the only way I could find that had some effect on the program execution or readable data