Use Timer2 with f_osc/12 input and Compare register 0 as interrupt source.
f_osc=20,000,000 Hz, f_osc/12=36,666.66 Hz
Suppose you need x % duty cycle.
Set the compare reg first duty= 36,666.66 * x/100 then on the IT set to 36,666-duty, then on IT again to duty etc.
If you need precision, then compensate the small error of 0.666: use i as a divide by 3 cycle counter, and apply 36666 if i=0 and 36667 if i= 1 or i=2.

Something like this (I am working in assembly, so my C is a shame...):

------------------

/* program sample, 10 % duty 50 Hz using Timer2, Q: 22 MHz */

#include "reg552.h"
#define Hz_50 36667 // 22,000,000/12/50
#define duty_cycle 3666 // 10 %

int i,p;

void main(void) {
TM2CON = 0x01; // 16 bit overflow IT: false
// byte overflow IT: false
// ext resetenable: false
// byte overflowT flag: 0
// prescaler: 1
// input: f_osc/12
IEN1 = 0x10; // T2 Compare register 0 IT enable, all the rest disable
IP1 = 0x00; // interrupt priority: low
CMH0 = duty_cycle / 256; // a compare0 register 1 msec-re állítva
CML0 = duty_cycle % 256;
EA = 1;
while (1);
}

// Timer2 Compare0 interrupt [0x5B]
void Timer2_int (void) interrupt 11
{
IEN1 = 0x00;
i++;
if (i==6) i=0;
TM2IR = 0; // clear flag
p = 256 * CMH0 + CML0;
switch (i) {
case 0: p = p+duty_cycle;
P1=0; // I forgot how to write P1.0 in C... :-)
break;
case 1: p = p+Hz_50-duty_cycle;
P1=1;
break;
case 2: p = p+duty_cycle;
P1=0;
break;
case 3: p = p+Hz_50-duty_cycle;
P1=1;
break;
case 4: p = p+duty_cycle;
P1=0;
break;
case 5: p = p+Hz_50-1-duty_cycle; //compensate
P1=1;
break;
};
CMH0 = p / 256;
CML0 = p % 256;
IEN1 = 0x10;
}