"...a frequency divider will always give me a 50% duty cycle"
Yes and it is right.
If you use common divider it give you really 50% duty cycle because divider respond to edges (ether rise or fall) of the input signal. I did'n write it explicitly in my previous contribution of the thread (I do apologize for that) and therefore I wrote there "If you can't use such way..." but in HW solving (not MCU dividing) is possibility to keying output signal. It hold for your "5 to 12% duty cycle" request only.
I describe example how I think it in little scheme below and by this way you can get duty cycle up to 25%.

       *------------*          *------------* 
       | *------*   | S100/100 | *------*   | S50/50
       *-|D    Q|---------*    *-|D    Q|--------*
         |      |   |     |      |      |   |    |
 PWM     |      |   |     |      |      |   |    |
 ------o-|CLK   |   |     o------|CLK   |   |    |
 200Hz | |      |   |     |      |      |   |    |
       | |    /Q|---*     |      |    /Q|---*    |
       | | R  S |         |      | R  S |        |  74HC11
       | *------*         |      *------*        |  *---*
       |  74AC74          |       74AC74         *--|   |  OUT 
       |                  *-------------------------| & |-------
       | *---------------*                          |   |
       *-|"Gate" delay !?|--------------------------|   |
         *---------------*                          *---*
       Switching 1's filtering

Michael,
if you cannot realise such HW design it will be better to switch to another solving of your problem instead.
I would to prefer Timer 2 solution to mentioned HW way because it is more flexible. We realised this way very precise output data streams as is POCSAG for example. You can also think about Peter's suggestion. Peter is guru I think.

HTH
Vaclav