The external reset signal is asynchronous to the internal clock .the RST is sampled during State 5 Phase 2 of every machine cycle .The port pins will maintain their current status for 19 oscillator periods after a logic 1 has been put on the rst pin,i.e. for 19 to 31 oscillator periods after the External reset has been applied
The internal Reset algo writes 0s to all SFRs except the port latches,the Stack Pointerand the SBUF,the port latches are initialized to FFH ,the Stack Pointer to 07H,and SBUF is indeterminate .The internal Ram is not affected by reset ,While the RST pin is high ,ALE PSEN/ are weakly pulled high ,it will take 1 to 2 machine cycles for ALE and PSEN/ to start clocking.