Ijaz,

I am using the parallel port. 3 Tri-state Octal D-FF's. one for the Lower Address Byte, one for the Upper Address Byte and the other for the Data Byte. Another D-FF (octal) is used to Control the above and supply the values for p2.6, p2.7, p3.6, p3.7, etc, etc.. I supply the req values to the Three Tri-state DFF's with out enabling the output. I enable the output as required by the algorithm. i.e. address first then the data, with the reuired time gap. so on so forth. like i said before i have verified that this data is available at the required pins, incuding the control signals

I have used a 317 to obtain the 5v/12v levels. the transistor used to switch between those two levels is a 2N3904.

I have not made any provisions for the input to the parallel port. I have used only the outp() fn in C.

I have given a delay of 5ms to account for the write cycle, instead of using the busy/ready bit.