I was trying to model the inout port of 8051 when suddenly i realized that testing of the inout port is not all that simple in VHDL. The inout port can have only one driver at one time and 8051 doesnt even have a signal like the output_enable for ports so that atleast the testbench will know that it can now write to the ports. There is always a conflict of drivers. Does anybody have any idea as to how to solve this. I read the intel manual and there is he has some two signals like read_pin and read_latch. Where and who is generating the read pin signal. Isnt the pin supposed to be always read. ie. isnt any change on the pin applied externally supposed to enter the latch and vice versa ????