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08/17/02 10:03
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#27399 - RE: inout port modelling of 8051
hi vishal;
you wrote:
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I read the intel manual and there is he has some two signals like read_pin and read_latch. Where and who is generating the read pin signal. Isnt the pin supposed to be always read. ie. isnt any change on the pin applied externally supposed to enter the latch and vice versa ????
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the same way as you would read any signal,
by giving a clock pulse and latching it.the clock pulse for read is generated internally when one issues read instructions.
read_pin and read_latch signal is generated depending on whether the instruction is simple read or read-modify-write.
some pins like interrupts are read every machine cycle.
i don't know a thing about VHDL.but are you sure there is no write signal in the port schematic?if i remember correctly there is a signal that writes to latch./q of latch
is used to drive load transistor.

regards
pranav



List of 4 messages in thread
TopicAuthorDate
inout port modelling of 8051            01/01/70 00:00      
RE: inout port modelling of 8051            01/01/70 00:00      
RE: inout port modelling of 8051            01/01/70 00:00      
RE: inout port modelling of 8051            01/01/70 00:00      

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