In that particularly mentoined that the address is latch at HIGH to LOW transition of the CHIP ENABLE ,and tha data is LATCH at LOW to HIGH transition of the CHIP ENABLE ..

Sorry, I could not see the datasheet of the chip. But is the address/data bus multiplexed on this chip?

I don't think this chip can be directly interfaced to 8051, since it is a 512K x 8 and would require some banking arrangement.