That's right...I divided the lower 128 bytes of the 8032 uC into blocks, 8 bytes allocated to each task to be precise (trying to speed up the switching operation by avoiding the use of external memory)

The actual task switching operation is performed in the Timer 2 ISR. So I get that the aforementioned registers are adequate to preserve the state for each task with perhaps the addition of the B register as well.

The only problem I am facing yet is some kind of priority implementation for each task whereby each task is given a value and is dispatched on its priority using some kind of algorithm for the Interrupt level handler routine. The OS is being developed on 2 boards, namely Cygnal 8051F015 and Flite-32 (based on the Intel 8032AH uC) using Keil Cx51, A51) Any ideas? Thanks.