Well Jeff:
If I was doing it I would simply haul out the oscilloscope and measure the timing of the A/D serial I/O signals on the processor pins and adjust the delay till the timing was matching the data sheet requirements.

If you don't have an o-scope then you have to resort to the analytical approach. Computing the timing depends a lot on what processor you are using. Various 8051 derivatives have different ratios of the crystal frequency to the instruction cycle rate.

Let us assume for the moment you have the old Intel equivalent 8051 where the crystal is divided by 12 to get the instruction cycle rate.

The MOV R7,#50 is a 1 cycle instruction.
The DJNZ R7,Delay_loop is a 2 cycle instruction executed R7 times.
The RET instruction is a 2 cycle instruction.

A cycle @11.0592Mhz/12 = 1.085 uSec.

Thus the delay due to your subroutine is as follows:
(1 + R7*2 + 2)*1.085 uSec.

Using R7 as a value of 50 as in your first code example results in this being a delay of nearly 112 microseconds. The delay actually is a little longer than this by a couple more uSec because we did not include the time needed to execute the Call instruction to the delay subroutine. All in all it does not seem like a very short delay at all!!! You may want to consider changing your code to eliminate the calls to the delay routine in the serial clocking routines and use a sequence of NOP instructions instead, keeping in mind that each one takes a little over 1 uSec to execute.

It says in the data sheet that the SCLK low time and high time minimum (fastest permitted) is 200 nSec (same as 0.2 uSec). If you are indeed using a processor with divide by 12 operation it seems to me that you do not want to have any delay at all in your clocking sequence. Just bit bang it as fast as you can. Even at this "as fast as you can go rate it is going to easily be possible to meet that Tacq time which for the MAX1112 is 1 uSec (The period from end of clock 6 to end of clock 8).

Now of course if you are using one of those new Cygnal parts that are blazingly fast with 25 MHz crystal and one clock per instruction cycle (40 nSec / cycle) then some delays would definately be required.

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You did not comment about what I said in my earlier post about your code. Why do you have the MOV R6,6 instruction in the Extra_Clocks loop?

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Another suggestion for you code. Maxim seems to think it is a good idea to shift zeros to the A/D converter for the clocks 9 - 24. In your example you have set P1.4 as a 1 due to tke low bit of the config bit being a 1. You should add an extra clear of the P1.4 pin after the instruction "DJNZ R6,Sensor_0_Loop".


Please reply....

Mike Karas