CMOS gates are made of MOSFETS so they can be paralleled to give higher drive currents
I would strongly recommed against such a practice (the fact that something "works" neither makes it safre or right).
If, for instance, you parallel two HEF4012 and one is just fast enough to pass (Tplh = 140ns) and the other is a bit faster that the "typical" (min not specified) let us say 50nS. In this case you will have a virtual short for 90ns every time the input switches. I can only guess what stress that will put on the chips.

Erik