Paul:
These days with CMOS Microcontrollers, CMOS Latches, and CMOS Decoders being used to drive RAM and/or FLASH chips (which are also most likely CMOS) the number of chips that can be used relates primarily to two factors.

One of these is the amount of capacitance on each bus and/or control line. Each particular chip output is specified to meet its data sheet timing characteristics at a particular load capacitance. For example a chip may be specified to meet data sheet timings when driving a load of say 70 pF. The input of each chip connected to this output will contribute a certain amount of load capacitance. The PC board traces themselves also contribute some capacitance. As long as the sum of all the input capacitances being driven plus the PC trace capacitance does not exceed the capacitance specified in the data sheet for the driver of the node than that driver part should be able to meet the specified timings.

The second issue that needs to be considered is the timing of the circuit as a whole while taking into account the delays through chips, data setup and hold timing requirements, and access time parameters. It is beyond the scope of a quick post on this forum as how to perform detailed timing analysis for a digital circuit but it is important to note that it is essential this analysis be performed on a design to ensure that a circuit will perform in a reliable manner. It is important to note that microcontrollers and the attendant RAM chips always seem to be pushing the performance envelope. Chips keep geting faster and faster and each new design should be analyzed carefully. It is not suitable to take old experience of a 1990's vintage design with an 8032 interfacing to a 6116 type RAM chip and try to build a system with the newest type components without re-evaluating the timing issues.

It is important to take a look also at the DC loading of the bus lines as relates to the static high and low voltage levels acheved at the outputs when taking into account the sum of DC loads contributed by all the inputs being driven. This requires analysis of the V_OH, I_OH, V_OL, and I_OL, parameters of the driver and the V_IH, I_IH, V_IL, and I_IL parameters of each driven input. You will find however that this static voltage level analysis usually does not expose a performance limiting factor in an all CMOS design like it used to in the days when circuits used a significant number of bipolar type logic chips. hat sais however there are instances in CMOS designs that need to be studied. There may be resistors, transistors, or other components connected to the node under study that will either contribute to the source or sink capability of the node driver or that may add additional load on the driver.

The most important aspect of static voltage level analysis these days, especially in the realm of ever lowering V_CC levels, is to make sure that drivers can drive the nodes to low enough low voltages and high enough high voltages to ensure that the driven inputs are forced into their guarenteed respective high and low levels. The difference between the voltage that can be placed on a node by a driver and the voltage level required by an input that is being driven is known as the "margin voltage". It is essential that any design have margins that are better than zero. The reason for this is that any noise voltage on a signal line or any differential noise between the driver chip and the receiving chip V_CC or GND lines eats into the available signal margin voltage. For example, if a node in the low level state had a data sheet derived margin voltage of 0.5 volts between the driver and the driven input, then noise spikes on the GND bus, as measured from the driver chip GND pin to the receiver chip GND pin, that exceed 0.5 volts may make the driven chip operate in an erratic manner.

A last comment I would like to make here relates to the driver chip output impedance. Chips with low output impedance are much better at driving nodes with more CMOS input nodes where the loads represented by the inputs are primarily capacitive in nature. Most data sheets for digital parts do not specifically specify output impedance for the drivers on a chip. Thus it is important to understand that the output impedance generally has two different values, one when the driver is attempting to pull a node to a high level and the other when the driver is attempting to pull a node to a low level. The high level output impedance is related to the V_OH that an output can achieve at a given specified sourcing I_OH current level. Correspondingly the low level output impedance is related to the V_OL that an output can achieve at a given specified sinking I_OL current level. It is important to note however that choosing circuits with the lowest output impedances (highest source / sink capabilities) is not always the best option. The lower the output impedance and / or the higher the load capacitance on the driver the more possibility that the circuit will generate unacceptable levels of noise. The noise can exhibit itself as any one or more of ringing on the signal line, coupling to other signal lines, spikes on the GND bus, or spikes on the V_CC connections. Any engineer who has experienced the difference between using a 74HC373 versus a 74ACT373 on a circuit board can full appreciate the effects of different output impedances.

I hope that this writing helps to show that performing the design of a digital circuit requires a bit of real engineering work in reading specifications, performing analysis and doing calculations if a reliable product is to be achieved. As such it is not sufficient to ask the question, "How many RAM chips can be used with the 74HC373 and the 74HC138?"

Michael Karas