If I can throw in my two cents as well. In general it is a good idea to take steps to keep any pin on the micro from being exposed to voltages over Vcc+0.4 volts. (Except in cases of 3.3V parts with 5 volt tolerant inputs). There are many things which could cause an input to go over the power supply pin.

Of particluar concern is when the Vcc to the micro falls toward ground during a power down situation or a momentary power outage. Under these times even signals that were below Vcc during normal operation could end up over the Vcc pin voltage as the micro powers off.

The inputs that could see these conditions are ones that are connected to other power sources that are still active whilest the micro supply is not. For example an A/D pin connected to a battery via a voltage divider.
Another is a charged capacitor that is connected to a pin.

These conditions can lead to latchup on the chip. Note that latchup on a chip CAN persist on a CMOS chip for minutes after a powerdown. I have seen it a number of times. One design I helped a guy recover from latch up problems had some Lattice GALs that the power up latchup persisted, if the parts were left in their socket, for more than 4 hours.

The best fix for latch up is to prevent the conditions mentioned above by the nature of the design. A good technique is to isolate a pin from the persistant voltage node by a series resistor of 10K or more. The attach a shottkey diode such as BAT54 from pin to Vcc pin. The anode side of diode to signal pin and cathode to Vcc pin.

Also note that as parts get faster and faster and the Vcc operating levels get lower and lower the chips are getting smaller and smaller. Thus the geometries on board are smaller. I think that that makes the chip more sensitive to latchup.

Michael Karas