| ??? 03/09/03 10:37 Read: times |
#41138 - 89c51RD2 for 56 Digital I/O - Jez & CPLD Responding to: ???'s previous message |
True. 26 chips IS a nightmare - but till date I have not had the "opportunity" to go all out for the 128 I/Os and have hence kept my sanity intact. In the current design I have kept the data and control bus on a 20Pin FRC header and add 16 I/O s at a time as per need. The CPLD is defenitely a good option and am currently getting the grips on it - should be able to get there fast. Raghu |
| Topic | Author | Date |
| 89c51RD2 for 56 Digital I/O | 01/01/70 00:00 | |
| RE: 89c51RD2 for 56 Digital I/O | 01/01/70 00:00 | |
| RE: 89c51RD2 for 56 Digital I/O | 01/01/70 00:00 | |
| RE: 89c51RD2 for 56 Digital I/O | 01/01/70 00:00 | |
| RE: 89c51RD2 for 56 Digital I/O | 01/01/70 00:00 | |
| 89c51RD2 for 56 Digital I/O - Jez & CPLD | 01/01/70 00:00 | |
| RE: 89c51RD2 for 56 Digital I/O - Jez & CPLD | 01/01/70 00:00 | |
| RE: 89c51RD2 for 56 Digital I/O | 01/01/70 00:00 | |
RE: 89c51RD2 for 56 Digital I/O | 01/01/70 00:00 |



