Raghunathan:
Here are my suggestions:

1) Use 4 each of part number 74HC150 16-1 mux. Connect the outputs of the 4 mux chips to four input port pins. The allocate 4 more output port pins as the A-B-C-D select pins that go all four if the mux chips. This solution takes 4 chips total and uses 8 port pins. Random access to any bit takes a single nibble select output and a read of the corresponding selected input nibble. This solution is cool becasue since port are bit addressable you can select a nibble and then perform various bit level tests of the input bits.

2) Use 8 each of part number 74HC165 eight bit parallel load shift register. Wire the registers into a pair of cascades each 32 bits long. (i.e. create two equivalent 32-bit shift registers). Wire the serial outputs of the two cascades to 2 input port bits. Allocate two additional output port bits which are wired to each of the SCLK and LOAD on all 8 of the chips. Serial access to all data is handled by pulsing the LOAD input to the shift registers. Then the SCLK output is pulsed 32 times while for each clock the 2-bits on the input port lines is read and stored internally. This solution takes a total of 4 port pins. If your not hung up on speed you can make the shift register cascade 64 bits long and then get by on a total of 3 processor I/O pins.


Hope these give you some alternatives to think about.
Michael Karas