If anyone is interested I have implemented a hardware manchester codec which can run at 12Mbit/second using the slowest rated xilinx
XC95xxXl series device,The receiver stage recovers the clock from the bit stream using a counter type algorrthm rather than a PLL.
I don't know what the maximum data rate is as I havent played with the timing constaints yet,but I should imagine that the master clock which runs at 8 times the data rate should be able to go upto about 200 Mhz quite easily.