| ??? 03/30/03 19:21 Read: times |
#42571 - RE: Video Capture Responding to: ???'s previous message |
There are any number of boards on the market called Frame Grabbers. Use www.google.com with frame grabber.
You could also consider making your own frame grabber mechanism by using a combination of a chip like the Brooktree Bt827 Video Decoder, a cleverly programmed smallish FPGA from Altera or Lattice, and a memory array with a couple of Megabytes. The interface to the 8052 side can be handled through the FPGA. The Video Decoder will accept NTSC or PAL video in analogue format and convert it to a 16-bit wide YUV encoded digital format pixel data. The FPGA programmed logic can contain sync detectors and address counters for the RAM array and store the video image into the memory. To make the design simple use SRAM with a fast cycle time. If you can arrange the design carefully the cycle time of RAM could be twice as fast as the cycle time of data from the video decoder. One way to achieve this is to accumulate two 16-bit values from the video decoder and write them both at once to the memory in one 32-bit wide write cycle. You can organize the other 1/2 of the memory bank bandwidth to permit the 8051 acess to the memory in an random access format. The 8052 interface would be most efficient if you used as the external RAM bus to provide up to 16 bits of the addressing. Since the video frame is bigger than 64K bytes you can implement the bank paging in the FPGA. The memory wants to be organized 2 times as big as one video frame. This way you can store the most recent frame(s) into one page while the 8051 can access the other page for looking at the memory image. When the 8051 is done with looking at the current frame (which may span many video frame stores in the opposite 1/2 of the RAM) it can toggle a flopflop in the FPGA that will freeze the most recent frame in the capture page and permit the decoder to start storing into the page the 8052 just finished with. The switch over needs to be synchronized with the video vertical sync pulse so that the last full frame is available. For low speed applications it may also be possible use a single video page of memory. Here the 8052 would wait till the frame store was finished and then the store/capture process would be turned off and then the memory would be available to the 8052 for as long as the image evaluation. You can expect the process of image evaluation using an 8052 to be relatively slow depending upon the type of algorithm you come up with. Michael Karas |
| Topic | Author | Date |
| Video Capture | 01/01/70 00:00 | |
| RE: Video Capture | 01/01/70 00:00 | |
| RE: Video Capture - Michael | 01/01/70 00:00 | |
| RE: Video Capture - Michael | 01/01/70 00:00 | |
RE: Video Capture | 01/01/70 00:00 |



