I think you are grossly under estimating number of required flipflops and/or logic cells need to implement a UART function. I have not implemented one but I checked at the Triscend Web site at this link:

Fast Chip IP Module Library

And they say that:

Hardwired Baud Rate Generator (12 CSL Cells)
Programmable Baud Rate Generator (21 CSL cells)
Half-UART - Receive (34 - 152 CSL Cells)
Half-UART - Transmit (22 - 146 CSL Cells)

The simplest configuration takes 68 CSL cells. I think you would need a CPLD or small FPGA with at least 128 logic cells.

Sometimes it is possible to buffer the X2 pin of a processor with a high impedance CMOS buffer to derive a clock with which to drive other circuits. The X2 pin may not have full logic swings however and you may need to bias the CMOS buffer into an amplifier (use an inverter) by connecting its output back to the input through a 1M or 10M ohm resistor.

I usually resist the tempation to do this in a design and instead outfit the board with a can type oscillator instead of just a crystal. The buffered oscillator can easly drive the CPU X1 pin and another circuit such as your CPLD.

Michael Karas