In the absence of many points on the hardware hook up , here is what you can try out : ( It is presumed you have a clock feed to the ADC within data sheet recommendations)

mov p0,#0ffh
clr p3.3 ; select channel zero - assuming that pins B and C of the ADC are also LOW

clr p3.4 ; enable ALE
nop ; Ensure a minimum of 1 micro delay. Assumed 12Mhz/12Clk.
setb p3.4

setb p3.0 ;enable soc
nop
clr p3.0

Most probably your problem starts here. After the setb p3.0, the EOC pin remains High for a long time ( tEOC ), so you will fall straight to "here1" and when the actual conversion starts, you are out of "here1" and ready to read !!

So I have altered that logic as beow.

here: jb p3.6,here ;wait till EOC goes low.
here1: jnb p3.6,here1 ; wait for conversion

setb p3.2
mov a, p0 ; OE must be high when you read..
clr p3.2


Unless you have some serious hardware bug / bad chip / bad clock, the above code SHOULD work.

Raghu