Hallo Hans,

you wrote:
'Also, the "Bible" states quite a different reason for the strong pullup to be activated while conducting normal I/O than charging capacitive loads.'

May I recitate from 'PHILIPS 80C51 family hardware description'?

'If the change requires a 0-to-1 transition in Port 1,2 or 3, an additional pullup is turned on during S1P1 and S1P2 of the cycle in which transition occurs. This is done to increase the transition speed. The extra pullup can source about 100 times the current that the normal pullup can.'

And isn't it right, that just capacitive load drastically decreases transition speed?
Maximum load capacitance is specified to about 80pF for Ports 1,2 or 3. Assuming that strong pull-up is comparable to classical HCMOS output, it can be assumed to have about 100 Ohms, perhaps even less.
When it's stated in hardware description that strong pullup is 100 times stronger than normal pullup, normal pull-up must represent a much bigger source impedance. Let's assume having only 1kOhm, then in combination with 80pF load capacitance an RC-delay is formed with a time constant of 80nsec! But, this time needed is only enough to charge capacitive load up to 63%. For charging up to 95% a much bugger time is needed: About 3 x 80nsec = 240nsec.
Such a transition time would be absolutely inacceptable. The more when even a higher source impedance is assumed. So, a strong pull-up indeed is needed. Assuming the 100 Ohm of above, 24nsec transition time is achieved, which just is observed in reality.
Are two periods of switching-on strong pull-up enough to achieve increase of transition speed? At 33MHz oscillator frequency two periods give 61nsec. So, well enough to do it's job.

Bye,
Kai