Yeah Harnam,

Scheme looks OK though I have not gone through pin-by-pin. I am sure you would have taken care of those.

I can make one suggestion. In such memory mapped I/O schemes, it is better to use one 74138 for all Input address decoding and one 74138 for all Output address decoding. Then you can wire the A10 to A12 bits to both 74138s and use the #RD and #WR ( with propoer inversion if required )to select read and write addresses. This scheme can handle expansions upto 8 address each for read and write without additional chips.

Raghu