Hello all,

going through my new planned design witch will be a P89C668 I have some questions.
For the system I need some memory mapped devices. For these devices it is sufficient for me to have 8 address lines. So if the nearly 8k internal ram and flash memory of the processor is enough for me want to switch off the ALE signal (AUXR A0=0).
Give now ALE a 1/3 squarewave signal of the oszillator frequency 4Mhz with a 12Mhz cristal?

So if I now access external DATA greater then the internal RAM of 8k what signals are on Port2? Already the high address byte if ALE is switched off? I what use this for chip select so I don't need a latch with the ALE.

What is the state of Port2 if external memory is not accessed or internal RAM is accessed? Is this high impedance or output?

In the rest of the circuit I can user 12Mhz clock of the cristal. Will it work to put the X2 cristal output to a buffer and use this for further clocks or will there the danger of getting wrong and shifting system clocks in the prozessor for production variing in the chips?

Bye
Wolfgang Rapp