Are you keeping the -CS pin of the SRAM chip tied to ground all the time? During run time, if you are operating solely on battery power, you should design to permit the -CS pin to go high between access cycles to RAM. When your system is inactive the lowest power mode of the SRAM is attained when the -CS line is not at active level. Even better is that if your system is in the power down mode with the SRAM in battery back up mode is to reduce the Vcc of the SRAM to lowest possible. These SRAMs which normally operates at 5V can backup with VCC lowered to a lesser level than 5V. You need to check the data sheet for the specific part you are using to see how low thus backup voltage level can go.

Also be aware that there are many different versions of 8Kx8 SRAMs. Some versions are optimized for very low standby current and others are not. Once again compare data sheets.

Michael Karas