Aha, I have caught your idea... but somehow I do not understand (=
Really, for example, I have 8-bit PWM byte array sequence.
With classic scheme we configure a PCA channel to PWM mode and load each byte into CCAPnH for a time defined by requested freq (usually, I control it via one more PCA channel worked in 16-bit compare mode).
The limit is caused from the fact that it is 8-bit PWM. As result, each time slot (and so frequences) must be with modulo-256 of input freq otherwise it is not possible to make correct output duty cycle.
Now about your idea - we select channel 0 for High Speed Mode. To be compatible with 8-bit PWM we still need to make output toggling with full cycle at least of 256 clocks (256,512,768 etc). So, what we have: input clocks of all PCA modules are the same; full output cycle must be at leat 256 input clocks. As result I do not see a way how does high speed mode helps with tuning frequence. Only way I see is usage not 8-bit but 7/6/5... resolutions instead. But it makes output quality lower :(
Good days!