| ??? 10/16/03 20:28 Read: times |
#56778 - Expanded I/O - timing? |
I am developing a specification for a new control system that requires expanded I/O similar to another recent thread.
It has at least 50 user keys, a few analog and digital inputs, and at least 50 outputs. The previous version of this product used an 80C320 with a PLD and memory mapped I/O, LCD, Keypad, RTC. Now I am considering the uPSD or Cygnal chips that have built-in FLASH, SRAM, and Logic. I am also considering using I2C chips for I/O and analog inputs. For budgeting software overhead, can anyone tell me about what to expect for a number of CPU cycles or microseconds (at 11 MHz) for accessing an I2C I/O peripheral like the MAX 6956? Thanks! |
| Topic | Author | Date |
| Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
| RE: Expanded I/O - timing? | 01/01/70 00:00 | |
RE: Expanded I/O - timing? | 01/01/70 00:00 |