Or you can do it in an ickle cpld like this....


-- Registers:
-- [Name] [Addr] [7] [6] [5] [4] [3] [2] [1] [0]
-- Status x0 0 0 0 0 0 0 TOG RF
-- Control x1 IE EN 0 0 0 0 0 0
-- System x2 0 0 0 S4 S3 S2 S1 S0
-- Command x3 0 0 C5 C4 C3 C2 C1 C0
-- TOG - Toggle, Shows the state of the received toggle bit
-- RF - Register Full, High when new data is available
-- IE - Interrupt Enable, Generate an interrupt when the
-- decoder is enabled and data received
-- EN - Enable, Enable/disable the decoder
-- Sx - System, The 5 System bits of the received RC5 code
-- Cx - Command, The 6 Command bits of the received RC5 code


library ieee;
use ieee.std_logic_1164.all;

entity rc5 is
port( clk :in std_logic; -- Clock signal, phase not relevant
rst :in std_logic; -- Negative logic reset signal
rd :in std_logic; -- Negative logic read signal
wr :in std_logic; -- Negative logic write signal
cs :in std_logic; -- Negative logic chip select
int :out std_logic; -- Negative logic interrupt output
addr :in std_logic_vector(1 downto 0); -- Address bus input
data_in :in std_logic_vector(7 downto 0); -- Data bus input
data_out :out std_logic_vector(7 downto 0); -- ... and output
rc5 :in std_logic); -- the infrared data input
end entity;

architecture rtl of rc5 is
-- Update this line with the system clock frequency in Hz.

constant SYS_CLK :integer := 200000; -- Example: 200kHz

-- Calculate the number of clock cycled in each RC5 bittime
-- (which is 1.778ms)
constant CLKS4BIT :integer := SYS_CLK / 562;

constant BUSOFF :std_logic := 'Z';

type STATES is (IDLE, START, TOGGLE, SYSTEM, COMMAND, FINISH);
signal state :STATES; -- States for the RC5 data frame
signal interstate :integer range 0 to 1;
signal clk_en :std_logic; -- Sample clock start and enable
signal bit_cnt :integer range 0 to 5; -- Counter for data bits
signal sys_buf :std_logic_vector(4 downto 0);
signal sys_reg :std_logic_vector(4 downto 0);
signal com_buf :std_logic_vector(5 downto 0);
signal cmd_reg :std_logic_vector(5 downto 0);
signal toggle_buf :std_logic;
signal toggle_reg :std_logic;
signal reg_full :std_logic;


signal enable_bit :std_logic;
signal int_enable :std_logic;


signal cnt :integer range 0 to CLKS4BIT;
signal sample :std_logic; -- Sample clock
begin
Decoder: process(rst, clk)
begin
if(rst = '0') then
sys_reg <= (others => '0');
cmd_reg <= (others => '0');
toggle_reg <= '0';
clk_en <= '0';
interstate <= 0;
state <= IDLE;
elsif(rising_edge(clk)) then
if(state = idle and rc5 = '1' and interstate = 0) then
clk_en <= '1';
interstate <= 1;
end if;
if(sample = '1') then
interstate <= interstate + 1;
case state is
when IDLE =>
interstate <= 0;
if(interstate = 1) then
if(rc5 = '1') then
state <= START;
else
clk_en <= '0';
end if;
end if;
when START =>
if(interstate = 0) then
if(rc5 = '1') then
state <= IDLE;
clk_en <= '0';
end if;
else
if(rc5 = '0') then
state <= IDLE;
clk_en <= '0';
else
state <= TOGGLE;
end if;
end if;
when TOGGLE =>
if(interstate = 0) then
toggle_buf <= not rc5;
else
state <= IDLE;
interstate <= 0;
if(toggle_buf = rc5) then
state <= SYSTEM;
bit_cnt <= 0;
end if;
end if;
when SYSTEM =>
if(interstate = 0) then
sys_buf <= (not rc5) & sys_buf(4 downto 1);
else
interstate <= 0;
bit_cnt <= bit_cnt + 1;
if(sys_buf(4) /= rc5) then
state <= IDLE;
end if;
if(bit_cnt = 4) then
state <= COMMAND;
bit_cnt <= 0;
end if;
end if;
when COMMAND =>
if(interstate = 0) then
com_buf <= (not rc5) & com_buf(5 downto 1);
else
interstate <= 0;
bit_cnt <= bit_cnt + 1;
if(com_buf(5) /= rc5) then
state <= IDLE;
end if;
if(bit_cnt = 5) then
state <= FINISH;
end if;
end if;
when FINISH =>
if(interstate = 0) then
if(rc5 = '1') then
state <= IDLE;
end if;
else
state <= IDLE;
clk_en <= '0';
if(rc5 = '0') then
sys_reg <= sys_buf;
cmd_reg <= com_buf;
toggle_reg <= toggle_buf;
reg_full <= '1';
end if;
end if;
when others =>
state <= IDLE;
interstate <= 0;
end case;
end if;
end if;
end process Decoder;

ReadOut: process(rst, rd)
begin
if(rst = '0') then
data_out <= (others => BUSOFF);
elsif(falling_edge(rd)) then
if(cs = '0') then
case addr is
when "00" =>
data_out <= "000000" & toggle_reg & reg_full;
when "01" =>
data_out <= int_enable & enable_bit & "000000";
when "10" =>
data_out <= "000" & sys_reg;
when "11" =>
data_out <= "00" & cmd_reg;
when others =>
null;
end case;
else
data_out <= (others => BUSOFF);
end if;
end if;
end process ReadOut;


Write: process(rst, wr)
begin
if(rst = '0') then
int_enable <= '0';
enable_bit <= '0';
elsif(rising_edge(wr)) then
if(cs = '0') then
case addr is
when "01" =>
int_enable <= data_in(7);
enable_bit <= data_in(6);
when others =>
null;
end case;
end if;
end if;
end process Write;

ClockGen: process(clk_en, clk)
begin
if(clk_en = '0') then
sample <= '0';
cnt <= 0;
elsif(rising_edge(clk)) then
sample <= '0';
cnt <= cnt + 1;
if(cnt = CLKS4BIT) then
sample <= '1';
elsif(cnt = (CLKS4BIT * 3)) then
sample <= '1';
elsif(cnt = ((CLKS4BIT * 4) - 1)) then
cnt <= 0;
end if;
end if;
end process ClockGen;

Interrupt: process(rst, cs, rd, reg_full)
begin
if(rst = '0' or (cs = '0' and rd = '0')) then
int <= '1';
elsif(rising_edge(reg_full)) then
if(int_enable = '1') then
int <= '0';
end if;
end if;
end process Interrupt;
end rtl;