Straight from the horses mouth (the 932 User's manual):
CPU CLOCK (CCLK) MODIFICATION: DIVM REGISTER
The OSCCLK frequency can be divided down, by an integer, up to 256 times by configuring a dividing register, DIVM, to provide
CCLK. This produces the CCLK frequency using the following formula:
CCLK frequency = fOSC / (N+1)
Where: fOSC is the frequency of OSCCLK
N is the value of DIVM.
Since N ranges in 0 - 255, the CCLK frequency can be in the range of fOSC to fOSC/256.
This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption.

Why, OH why did Juan not look there before posting?
-1000

Erik