Hallo Patrick,

internal to most all CMOS inverter stages are two parasitic bipolar transistors, one pnp and one npn. These parasitic bipolar transistors are naturally configured as a thyristor! These transistors conduct when one ore more of the pn junctions become forward biased. When this happens, each parasitic transistor supplies the necessary base current for the other to remain in saturation. This is known as 'latch-up' condition and can possibly destroy the device if the supply current is not limited.

To trigger the thyristor there must be a voltage at output of inverter greater than Vcc + 0.5V or less then -0.5V. And, there must be enough current!!

Fatal is the following: If you measure with a voltmeter (diode testing range), whether there are internal protection diodes from output to Vcc and 0V, then you will indeed detect the voltage drop of a pn-junction. But this is NOT caused by a protection diode, but from parasitic thyristor!!!!!

It is not possible to eliminate latch-up completely. The only alternative is to impede the thyristor from triggering. By the introduce of additional guard structures, minimum current to trigger parasitic thyristor can be highly increased. For 74HCMOS to about 450mA at 25°C and 250mA at 125°C.

In datasheet you will find a hint, if there is a latch-up protection implemented: Maximum currents into output and out of output for the case that output voltage is greater than Vcc or less than 0V are specified! If there is no such maximum output current specification, but only the maximum rating not to apply a voltage at pin above Vcc + 0.5V or less than -0.5V, then you must be very careful!!!! You should never bias the internal parasitic thyristor which looks like a set of protection diodes!

A good measure against latch-up is the introduce of Schottky-diodes from output pin to Vcc and 0V. Because of the metal-silicon junction of Schottky-diode voltage drop across a biased diode is some 100mV lower than that of the pn-junction of parasitic thyristor. Also, this Schottky-diode will faster turn-on, than the parasitic thyristor needs to be triggered. These two points highly reduce the trigger current for parasitic thyristor. Probability of latch-up is highly decreased.
Additional measures against overvoltage are of benefit. So, when micro's pin is connected to outer world the use of transzorb, varistor or even simple filter capacitance in combination with a current limiting resitance is highly recommended.

Some pins of micro do have internal protection diodes. If I remember correctly 'XTAL1' pin and 'RESET' pin. This seems quite natural, because these pins will experience overvoltages just by design.

Kai