Whilst I have not used the chip that you mention, I dare say a latch for the lower 8 address bits is required! The data and lower 8 bits of address is multiplexed therefore for the micro to do a read, it outputs the address then raises ALE to tell the hardware to hold (latch) the address, waits a little, drops ALE and lowers /RD, waits some time for the data to appear from the external device (ram chip in your case) and latches that data internally, raises /RD and that's the bus cycle finished.

Test the external ram by first setting the EXTRAM bit to the required state and testing to see if the external ram is working then try alternating the EXTRAM bit - there may be internal delays required although this is normally pointed out in the documentation.