| ??? 01/10/04 18:17 Read: times |
#62313 - RE: isdn Responding to: ???'s previous message |
The thing I would avoid trying to do on the microcontroller is a software implementation of HDLC but even a table driven design of that uses more FLASH than processor bandwidth. Not speaking as one who has done it, but if one were to use an 8051 derivative that has L1 (PHY) HLDC for bit stuffing and FCS, add some RAM for packet buffers, do you think that a LAPD implementation would be realizable? |
| Topic | Author | Date |
| isdn | 01/01/70 00:00 | |
| RE: isdn | 01/01/70 00:00 | |
| RE: isdn | 01/01/70 00:00 | |
| RE: isdn | 01/01/70 00:00 | |
| RE: isdn | 01/01/70 00:00 | |
| RE: isdn | 01/01/70 00:00 | |
RE: isdn | 01/01/70 00:00 | |
| RE: isdn | 01/01/70 00:00 |