Oh, what a confusing thread...

I'm missing some points here:

1. I miss a descriptive thread name.

Amjad, on posting site you were instructed to choose a descriptive thread name. Just 'Help Please!!!' is NOT descriptive.

2. I miss understandability of original post.

Amjad, what you posted was totally confusing. If your english is not so good, then you should at least try to post a schematic, so that we can help.

3. I miss your respectful behaviour to senior experts.

You wrote:

(1) yea i know iam bad at discription
(2) after the interupt happens i scan port 1 to see which button is pressed so it should all work
(3) you didnt say anything helpful till now
(4) seems you didnt understand what the problem is :D
(5) if you can help then go for it
(6) thank you ;)

Points (3) to (6) are arrogant and impudent! If you are not able neither to give any understandable description of what you mean, nor to give us a schematic or something else, then it's not our mistake, if we do not have any idea about what you want.

Also: Charles has spent time and energy to draw a schematic for you. Did you already say 'Thank you'???
It's not the first time, that Charles efforts to draw a schematic saved a thread from total confusion. Thank you, Charles, for the schematics you draw so often, because original poster was not able or not willing to do this!

4. I miss the discussion about 'positive logic' and 'negative logic'.

The most confusion about NANDs, NORs, ORs and other gates resulted, because it wasn't highligted up to now, that Amjads application is a typical 'negative logic' situation. (I appologize, if I have overlooked someone.)

Amjads application contains buttons, which deliver low level, when being active. And /INT input of micro also needs low level, when being active. So, all involved signals are low level, when being active, which means, that application works with 'negative logic'.

What gate circuitry is needed?
Let's name the button inputs 'A', 'B', 'C', 'D', 'E' and the output, which is connected to /INT input of micro, 'X'. Then, what is needed is a circuitry, which gives an active output, when 'A' is active or 'B' or 'C' or 'D' or 'E'. Because 'active' here means, that according signal is low level, following equation results:



This equation represents a 'NEGATIVE OR' gate, an OR gate for 'negative logic'. This is an OR gate with 'bubbles' at each input and at output. This is NOT a NOR gate!! A NOR gate would not have bubbles at each input, only a bubble at output.

Now, we ask: Is there any 'positive logic' gate circuitry, which results in the same truth table as this above NEGATIVE OR gate?
When we think about 'positive logic', then we expect an equation beginning with 'X = ...'. Well, we can expand the equation above and result with:



This equation expresses nothing else than DE MORGAN's theorem, and it represents a 'POSITIVE AND' gate, an AND gate for 'positive logic'.

Now, which gate to draw with Amjad's application? 'NEGATIVE OR' versus 'POSITIVE AND'?

'NEGATIVE OR' is the much better suited one. Why?
Because his application works with 'negative logic'! But, of course, an experienced person will also be able to read the POSITIVE AND gate. But then, he must know, that all inputs and the output are low level, when being active. So, he needs additional information, which he would not need if 'negative logic' symbols were used.
If in bigger systems 'negative logic' is used, then the consequent drawing of 'negative logic' symbols can be very very usefull!

Kai