I am using 32k*8bit CMOS SRAM chip.
So far
>A0 to A7 are connected to Q0 to Q7 on the latch
>A7 to A14 are connected to Port 2
>I/O1 to I/O8 are connected to Port 0
>Vss and /CS are grounded
>/WE is connected to P3.6
>LE on the Latch is connected to ALE
>/RD(P3.7) and PSEN are anded and brought into /OE on the RAM chip
>/OE on the latch is brought to /WR(P3.6)

Thanks for the help, sorry if I was a little vague
Tony