??? 02/26/04 21:35 Read: times |
#65580 - RE: Second Asyncrohnous Interface on 89c Responding to: ???'s previous message |
I am curious as to how much processor bandwidth would be used to run a receive only 4800 bits/second interface using a software UART. Sheikh has mentioned the 89C51 processor and it stands to reason that an 11.0592 MHz crystal is useful for a software UART for much the same reason as it is for using the normal hardware UART. If the particular species of 89C51 that he is using is one of the divide by 12 types then one can compute that there are 192 available software bus cycles per received bit into the sofware UART.
It seems quite reasonable to think that maybe 45 to 50 bus cycles per bit could be required to do the receive function. This translates into a bandwidth utilization of about 25% thus leaving the processor free to handle the rest of its functions 75% of the time. Michael Karas |
Topic | Author | Date |
Second Asyncrohnous Interface on 89c51 | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c51 | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c![]() | 01/01/70 00:00 |