??? 02/26/04 23:31 Read: times |
#65585 - RE: Second Asyncrohnous Interface on 89c Responding to: ???'s previous message |
I now looked at the routines that Charles linked to. I can see what Erik means about 100% duty cycle. When you send or wait for receive there is nothing else that the processor can do.
Maybe,,,,if Sheikh wants to be able to let the microcontroller perform other tasks while the software UART is doing its thing, similar to the way that the hardware UART works when used with interrupts, he would like to look at the Signal Labs App Note #115. This shows two examples, one in C and the other in Assembly Language, for a software UART implementation that is coded as a state machine that ticks through the receive and transmit sequences using a series of timer interrupts that regulate the bit rate. Here are links to the App Note and to the accompanying software archive. http://www.silabs.com/products/pdf/an115rev1_1.pdf http://www.silabs.com/products/...115_sw.zip Michael Karas |
Topic | Author | Date |
Second Asyncrohnous Interface on 89c51 | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c51 | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c | 01/01/70 00:00 | |
RE: Second Asyncrohnous Interface on 89c![]() | 01/01/70 00:00 |