hi,
because of RXD0 is sampled two clkout cycles before the rising clock edge on TXD0 , the recieving data is always wrong value in synchronous mode 0

that you said, is strange. Most shift registers I know, use rising edge for roll data. So such mode is common used, for example, with 74299 and 74323 without any problems.

Regrads,
Oleg