It all hinges on burst errors. The width of a burst error is the maximum distance between incorrectly transfered bits.

Transmit data 0x12 0x34, sending LSB of each byte first:

0x12 0x34
0100 1000 0010 1100

Feed data 0x12 0x34, into CRC MSB of each byte first:

0x12 0x34
0001 0010 0011 0100

Now, suppose that the transmission suffers a 4-bit burst error right in the middle - randomising the bits marked as 'e':

0x12 0x34
0100 10ee ee10 1100

These same bits as fed into the CRC:

0x12 0x34
ee01 0010 0011 01ee

The transmission has suffered a burst error of just 4 bits in width. A well designed CRC of length r will detect all burst errors of less than r in width. So, an eight bit CRC will be garanteed to detect this burst error.

However, the data was actually fed to the CRC generator in a different order to that in which the data was transmitted. As you can see, as far as the CRC calculator is concerned, the 4-bit physical burst error is a 16 bit burst error. Consequently, an 8-bit CRC is not garanteed to detect it.