First of all, excuse my poor english writing.

Consider the following case.

1. A background task was interrupted by a HIGHER LEVEL interrupt.
2. The return address was pushed into the stack and the ISR started.
3. In normal case we will have the ISR exit with a RETI.

As we all know that there is some interrupt logic inside the 8051 to stop a lower priority interrupt to interrupt a higher prriority one.

Here are a few questions:

While inside and ISR:

1. Will push or pop change the state of that logic circuit?

I think this should be a NO.

2. Will changing the value of the SP ( I mean changing the SP form say
from 0x80 to 0x90) change the state of that logic circuit (JUST THE LOGIC)?

I think this should be a NO.

3. Will changing the content that the SP pointed to ( the return address) change the state of that logic circuit?

I think this should be a NO.

4. If we use an RET instead of a RETI, will it changed the state of that logic circuit?

I think this should be a NO as well. ( It's mentioned in the SPEC)


We are know that no lower prioirty interrupt can interrupt before the current higher interrupt finished. And I think that we all agree that using just the RET, push ,pop , mainpulateingthe SP and the content of the STACK cannot and should not change the state of this interrupt logic.

As the state of the interrupt logic changed after an RETI, it indicates the RETI besides putting the right address into the PC, is also performing a function that change the state of the interrupt logic.


Now, can you manipuate the stack so that you can go back to the address while it was interrupted without using the RETI?

Yes, you can, but that also means the logic state of the interrupt circuit
will not be reset. However, if the current interrupt is a low level one, then all other higher level interrupts can still function correctly.

Although I didn't check this with a real program.
I think the approach I took should indicate my answer to this question.

******** HOWEVER ************

1. Don't use software simulator to test this abnormal case. Software simulator may not have the "complete" interrupt logic built in and I think most software simulator were desinged for normal operations

2. While it is stated that an interrupt of the same level will not be serviced in an ISR. I am not 100% sure if it is allowecd to have the same interrupt twice (ie. timer 0 interrupt inside timer 0 ISR).

3. My suggestion is to test this case with a program having 2 higher priority interrupt and 1 low priority interrupt. Trigger one of the higher priority interrupt and instead of using RETI, manupulate the stack so that it "return" to the main program. Than check if BOTH the other two interrupts -one higher and one lower will work.

4. Try it with different chips from different manufacturer.