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???
04/26/04 17:40
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#69221 - RE: how can a slow pulse period be known?
Responding to: ???'s previous message
The way i would do it is to implement a large counter in a cpld which is started and stopped by rising edges and sets the interrupt when the count is finished so the counter value can be read by the 8052,this way the interrupt latency error is eliminanted.If you want ill post some vhdl to do this with a suitable 8052 interface for a cpld.

List of 9 messages in thread
TopicAuthorDate
how can a slow pulse period be known?            01/01/70 00:00      
   RE: how can a slow pulse period be known?            01/01/70 00:00      
   RE: how can a slow pulse period be known?            01/01/70 00:00      
      RE: how can a slow pulse period be known?            01/01/70 00:00      
         RE: how can a slow pulse period be known?            01/01/70 00:00      
            RE: how can a slow pulse period be known?            01/01/70 00:00      
               RE: how can a slow pulse period be known?            01/01/70 00:00      
   RE: how can a slow pulse period be known?            01/01/70 00:00      
      RE: how can a slow pulse period be known?            01/01/70 00:00      

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