OOPs colours went a bit strange,

---Simple 16 bit counter started and stopped 
---by the low frequency input divided by two.
--- with little state machine to implement a 8052 interface in 8 bit mode
---reading from the base address when the interrupt is low returns the
--- low byte of the counter,reading the base address+1 returns the high byte
--- of the counter and resets the interrupt.  
--- ignore the interrupt at reset,just do a dummy read to clear it
--- if you want the modelsim simulation waveforms as a postscript file mail me.

 library ieee;
use ieee.std_logic_1164.all;
ENTITY bidir IS
    PORT(
        bidir   : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        oe      : IN STD_LOGIC;
        inp     : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        outp    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END bidir;
ARCHITECTURE rtl OF bidir IS
SIGNAL  a  : STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL  b  : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN

        a <= inp;
        outp <= b;


     PROCESS (oe, bidir)
        BEGIN
        IF( oe = '0') THEN
            bidir <= (others=>'Z');
            b <= bidir;
        ELSE
            bidir <= a;
            b <= bidir;
        END IF;
    END PROCESS;
 end rtl;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;





entity C_interface is
    port(

^I    p_clk^I: in^Istd_logic;^I-- processor clk
^I    reset^I: in^Istd_logic;^I-- processor reset
^I    lps^I^I: in^Istd_logic;^I-- Long period signal to measure^I^I--- assuming 8 bit addressing mode,it makes things easier
            addr_data   : inout   std_logic_vector (7 downto 0);
            ale_n       : in    std_logic;
            psen_n      : in    std_logic;
            rd_n        : in    std_logic;
            wr_n        : in    std_logic;
^I    int_n^I: out^Istd_logic
                   );


end C_interface;

-- assuning that the test counter is 16 bits depending on the p_clk and stuff

architecture BEHAVIOUR of C_interface is

constant RESET_ACTIVE :std_logic:='1';
constant BASE_ADDR    :std_logic_vector(7 downto 0):=x"00"; -- set this to whatever
constant Base_addrplus1 : std_logic_vector(7 downto 0):=x"01";
type UC_STATE_TYPE is (IDLE, ADDR_DECODE, DATA_TRS, END_CYCLE);
signal uc_data_out  : std_logic_vector(7 downto 0);
signal timer:std_logic_vector(15 downto 0);
signal prs_state, next_state : UC_STATE_TYPE;
signal data_oreg_0,data_oreg_1,addr     : std_logic_vector(7 downto 0);
signal lpsdiv,uc_data_oe:std_Logic;
  component bidir
        PORT(
        bidir   : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        oe      : IN STD_LOGIC;
        inp     : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        outp    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
end component;

begin
divlps:process(lps,reset)
begin
^Iif reset=RESET_ACTIVE then
^I^Ilpsdiv<='0';
^Ielsif rising_edge(lps) then
^I^Ilpsdiv<=not(lpsdiv);
^Iend if;


end process;

bdir:bidir
^Iport map(bidir =>  addr_data,
^I^Ioe     =>  uc_data_oe,^I
^I^Iinp   =>  uc_data_out,
^I^Ioutp   =>  addr);^I


timr:process(p_clk,lpsdiv)
begin
^I
^Iif rising_edge(p_clk) then
^I^Iif lpsdiv='0' then
^I^I^I
^I^I^Itimer  <=(others=>'0');
^I
^I^Ielse
^I^I^Idata_oreg_0<=timer(7 downto 0);
^I^I^Idata_oreg_1<=timer(15 downto 8);^I
^I^I^Itimer<=timer+'1';
^I^Iend if;
^Iend if;
^I
end process;^I


gen_int:process(lpsdiv,prs_state)

begin
^I^Iif falling_edge(lpsdiv) then
^I^I^Iint_n<='0';
^I^Ielsif prs_state = end_cycle then
^I^I^Iint_n<='1';
^I^Iend if;
end process;^I^I^I


UC_SM_REGS: process (p_clk, reset)
begin
        if reset = RESET_ACTIVE then
            prs_state <= IDLE;

        elsif rising_edge(p_clk) then
            prs_state <= next_state;

        end if;

end process;


uc_if: process (prs_state,psen_n,addr,data_oreg_0,data_oreg_1, ale_n, rd_n, wr_n)

begin

next_state <= prs_state;
 uc_data_oe<='0';
 uc_data_out<=(others=>'0');
    case prs_state is
            when IDLE =>

^I^I^I^I^I
            if ale_n='0' and psen_n = '1' then
               next_state <= ADDR_DECODE;
            end if;



        when ADDR_DECODE =>
^I
^I    if rd_n = '0' or wr_n = '0' then
                        next_state <= DATA_TRS;
            else

                  next_state <= IDLE;
            end if;



        when DATA_TRS =>

^I^Iif rd_n = '0' then
^I^Iuc_data_oe<='1';
^I^I
^I^Icase addr is
^I^I^I when base_addr => uc_data_out <= data_oreg_0;
                         when base_addrplus1 => uc_data_out <= data_oreg_1;
^I^I^I when others => NULL;^I
^I^I end case;
^I
                end if;


                if rd_n = '1' and wr_n = '1' then
                    next_state <= END_CYCLE;
                end if;



        when END_CYCLE =>

^I
             if ale_n = '1' then
              next_state <= IDLE;
            end if;
^I^I^I

             end case;

end process;

^I
    end BEHAVIOUR;

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