Hallo Christian,

there's probably no other issue, where one can read so many contradictory publishings. Terrible...
Because of this, some years ago I made some numerical calculations to find out, what's really going on, if burden capacitances are omitted or what happens, if an additional series resistor between output and crystal is added, as some manufacturers recommend to their microcontrollers. And I found some very interesting details...

A crystal can be represented by the following equivalent circuit, which is shown for a 11.0592MHz quartz, but it's of general validity:



Here the first problems arise: Manufacturers give rather different values for these equivalent parts. So, I varied the values of involved parts a bit, but could not find relevant differencies.

Even without numerical calculation, with a bit experience in the analyzing of equivalent circuits, performance of this circuit above can be estimated very well.
Two resonance frequencies can be seen, a series resonance of Lq and Cq and a parallel resonance of Lq, Cq and Cp. Series resonance will happen at

fs = 1 / 2 / pi / SQRT(Lq x Cq) = 11.059MHz

Don't expect too many digits behind the point, given values for Lq and Cq are rounded, of course.

Parallel resonance will occur at

fp = 1 / 2 / pi / SQRT(Lq x (Cq x Cp)/(Cq + Cp)) = 11.063MHz

Cq and Cp are connected in series and because Cp is so much bigger than Cq, the series capacitance of both is only slightly smaller than Cq, resulting in a parallel resonance frequency only being slightly higher than fs.

When talking about LRC filter, I often give the criterium for avoidung resonance as

R >= SQRT(2 x L / C)

For the given quartz Rq should be about 10MOhm. But Rq is 30Ohm, which results in a very heavy and sharp resonance!

Even the phase versus frequency performance can be estimated without numerical calculation:

At frequencies lower than fs or higher than fp impedance of series circuit of Lq and Cq is much bigger than impedance of Cp. So, the crystal looks like a pure capacitor!

Between fs and fp situation is as follows:
At series resonance frequency fs series impedance of Lq, Cq and Rq decreases to a minimum and is identical to Rq. Because Rq is much smaller than impedance of Cp at this frequency, crystal looks like a resistor!
At frequencies higher than fs, but lower than fp, impedance of Lq dominates over impedance of Cq and Rq, and also dominates over impedance of Cp. So, crystal looks like an inductivity!
At parallel resonance frequency fp circuit becomes very high impedant and impedance is real, means crystal looks like a very high ohmic resistance!

If the crystal is mounted in a Pierce oscillator like this one



we can estimate the phase shift versus frequency performance:
If Rv = 0 and output impedance of gate (Rout) is negligible, phase shift between signal at output of gate and signal at input of gate is zero at frequencies lower than fs or higher than fp. Why? Because crystal looks like a capacitance.
At fs or fp crystal looks like a resistance and introduces a phase shift of -90° (phase lag!), means the circuit looks like a simple RC low pass filter (single pole).
Between fs and fp crystal looks like an inductance. So, phase shift is -180°, means thy crystal circuit looks like a LC low pass filter (two pole).

So, we are not surprised, when we see what the numerical calculation yields for the case that Rv and Rout are negligible. First the case where C1 = 1pF and C2 = 4pF, means only stray capacitance:



And then for the case where C1 = 34pF and C2 = 37pF, means using two 33pF burden capacitors:



What do we see in these plots?
Frequency range is 11.055MHz...11.065MHz. Phase shift is shown between -360° and +360°. Also an auxiliary line at -180° phase shift is shown. We also see the height of signal voltage at input of gate. And finally the heat dissipation of crystal, or by other words, crystal drive level .

Comparing both plots, we see that with negligible burden capacitance (load capacitance of crystal) series resonance frequency of built-in crystal is about 130ppm higher, than when using the 33pF burden capacitors!
But we see something more alarming, too: There's no frequency, where the phase shift is exactly -180°!!! Does that mean, that no oscillation will occur? Happily not. Up to now we havn't taken into consideration, that signal passing the gate suffers from propagation delay. Assume 10nsec propagation delay. Then, the signal gets an additional phase shift of 10nsec x 11.0592MHz x -360° = -40.0°. Then, only -180° -(- 40°) = -140° phase shift introduced by the crystal circuitry is needed to fullfill the oscillation criterium. But the faster the gate is, the more difficult it is to fullfill the oscillation criterium, especially, if additionally a crystal of lower frequency is used.

Even, if under these circumstances the crystal would start to oscillate, the circuit is not able to deliver a very precise frequency. Why? Because signal voltage at input of gate is so high, that signal would be clipped across internal protection circuitry. Signal voltage at input is just much too high!
Also, drive level of crystal is terrible high!! This drive level is pretty enough to destroy the crystal. Remember that drive level for a HC-18 crystal should not exceed 1mW!

All these problems can be overcome, when Rv or at least output impedance of gate (Rout) is increasing a bit. With Rout = 50Ohm, negligible Rv and with C1 = 34pF, C2 = 37pF, we get:



And if additionally Rv is increased to 220Ohm, we get:



Why is increasing Rv, Rout of benefit? Because an additional phase shift is introduced, which makes the phase shift curve pass the -180° line! Also, signal voltage at input of gate and, of special interest, crystal drive level decreases to a sane value. We don't need any longer the phase shift introduced by propagation delay of gate. Even a very fast gate will not have any problems to start to oscillate.

Finally, what would happen, if we again omit the burden capacitors? Have a look by yourself:



Everything is wrong again: Heavy deviation of oscillation frequency of about 130ppm, terrible high signal voltage at input of gate, resulting in clipping and degradation of precision of oscillation, AND needing especially high propagation delay of gate for fullfilling oscillation criterium. Only crystal drive level is a bit decreased, but is still too high.

If we now take into consideration, that many built-in Pierce oscillators of microcontrollers do already contain either an increased Rout of gate or an additionally implemented Rv, as poly-silizium resistor on die, not necesseraily intended to introduce additional phase shift, but to limit crsytal drive level, then the only recommendation can be:

DO NEVER OMIT THESE BURDEN CAPACITORS!

If manufaturer tells, that 27...33pF capacitors are needed from each oscillator pin to ground, then please do that. The measure is not to give the crystal its load capacitance, but to make the oscillator reliably work! So, if you have a crystal needing 18pF load capacitance, then do nevertheless connect 33pF capacitors to oscillator pins, if manufacturer of microcontroller tells you to do that. The only effect is a slight deviation of nominal oscillation frequency. But the oscillator will work!

Assume a manufacturer recommends the use of 27...30pF burden capacitors with 11.0592MHz crystal. Then, if in an application crystal frequency is chosen much lower (perhaps 4MHz), propagation delay time might not be sufficient to introduce relevant phase shift. Then, only the phase shift introduced by Rout/Rv will make the oscillator work! Then, it can be helpful to slightly increase burden capacitors (from 27pF to 33pF for instance). On the other hand, if crystal frequency is chosen very high (>24MHz) phase shift introduced by propagation delay of gate is very probably enough to safely fullfill the oscillation criterium. Then, it can be helpful to slightly decrease burden capacitors (from 27pF to 22pF for instance). Again, this has nothing to do with the crystal, but with the oscillator.

Needless to say at the end of this post, that layout of oscillator circuit must be routed very carefully. Do not introduce avoidable stray capacitance. All connections must be kept as short as possible.

Kai