There are several ways to make PWM waveforms with a PCA.

One way is to use the native PWM mode where the period of the PWM mode is determined by how long it takes the low byte of the main PCA counter (Philips calls it the CL counter) to cycle through 256 counts. The PWM period is then controlled by bit selections in the control register that selects the clocking for the main PCA counter. On the '669 chip this is selectable from choices of Fosc/2, Fosc/6, an Externally applied clock on a particular pin, or from the Timer 0 overflow. With the external clock or the Timer 0 overflow option the PWM frequency would be 1/256 of the applied frequency. With the Fosc options the PWM frequency is limited to a net value of Fosc/512 or Fosc/1536. So in this mode for a 3 KHz PWM frequency your T1 overflow or external clock input would have to be 768 KHz. Or you could run your processor at 1.536 MHz or 4.608 MHz.

The other way to generate PWMs with a PCA is to use the HIGH SPEED output mode wherein a full 16 bit mode is possible. The main PCA counter free runs with a count going from 0 to 65535. The 16-bit compare register for a particular PCA channel is set to a value to force the channel output to toggle when a compare match has occurred. In this scheme you configure an interrupt to software each time there is a match and then the ISR sets a new compare value for the next time the output should toggle. This requires two interrupts per PWM cycle and is a rather effective way to get a nice PWM with a large range of resolution. It clearly works better when the PWM frequency is a low as opposed to high. The scheme also has limitations if you try to do too many PWMs at one time in the PCA because of total processor interrupt load.

There is a modification of the above method that can also be used wherein the main PCA counter is set to generate a processor interrupt whenever it overflows. It is possible in this scheme to re-program the value of the main PCA counter in the interrupt such that the total period is less than the 65536 counts as described above. For slower clocking rates the PCA counter could be set to count for say 4000 clocks. If this mode is used the PCA counter overflow interrupt has the job of setting all the PWM outputs that are used to a particular output level. The same interrupt can then set the capture registers to appropriate values for the duty cycle of each PWM signal to be output from values stored in RAM. Each individual PCA channel in this method is set to HIGH SPEED OUTPUT mode and the output signal will toggle to the other state at match time. Using this scheme it is possible to make up to 5 PWM signals out of a single PCA module that are all synchronized using a single software interrupt per PWM cycle. The major drawback of this method is that there will be some possible jitter to the PWM cycle time as the software gets into the interrupt and re-programs the new value for the main PCA counter. The jitter can be eliminated through very careful programming as long as it is not necessary to produce PWM signals that go close to 0% or 100% duty cycle (say limited to a 10% to 90% range).

Hope all that helps.
Michael Karas