In answer to your question:
you can read the data after CE and OE are low, as the cpu fetch cycle is most probably slower than the access time of the ram chip. As for writing, the write data must be output before you assert WR (assuming you assert CE first). Again you probably don't need to wait as again the cpu instruction cycle is probably slower than the write time of the ram.

The main problem I can see is that you have no means of loading the address latch to load the lower 8 bit address. As for the general sequence of events - read the 8051 datasheets - they have nice pictures of the bus timing. Doing it via code is going to be a bit slower - I suggest you figure out a means of freeing the rd and wr port pins. Methinks that might just be easier - sounds like you're creating another problem to solve a problem. If you can tell us what you're really trying to do, I'm sure there'll be plenty of suggestions to solve the source of your problem.