There's that matter of "strong 0, weak 1" but as I know reliablity of that rule in some conditions is questionable and sometimes requires extra tricks (pull-ups etc) so I wanted to ask if this will work:

1) Instead of putting the AND gate between PSEN and RD, while connecting to external memory, if I simply connect the lines any of them going low should pull the line low, allowing common code/data memory. Right?

2) For serial programming purposes I need to keep PSEN low, EA and RST high.
If I run a pull-up through a switch to EA and RST and the same line through a negator to PSEN, I get the result with one switch, but once disconnected/grounded it will go high for whole runtime duration. PSEN or OR should be still able to sink it keeping solution (1) working. Right?

3) If I apply (1) and (2), won't RD sink my negator output while I try to keep PSEN high? (I haven't seen in data sheet what happens to RD during serial programming or reset...) Would applying resistors somewhere underway help?

4) If I connect EA and RST like in (2), but want to pull EA up, it would pull RST up too. Would a diode allowing current from direction of RST to EA but not opposite, (and eventually a very weak pull-down on RST side) suffice to protect RST from going high?

If you think I shouldn't bother with such matters and just put that extra AND gate, drag EA, PSEN and RST over 3 separate lines to a 3-channel switch or 3 separate jumpers, I will accept that as a perfectly fine answer too.

The chip I intend to use is DS89C420, if that helps (I'd like to know how harmful/harmless my ideas would be while using in any configuration though) - the application is to be a general purpose dev board with primary task of programming and testing eeproms, NVRAMs and such for other boards, so it should be able to run both from internal flash and from external memory and be easy to program or receive data from PC.