hi,

Raj, that schematic you have mentioned on, is free of such problems. In fact, described problem appears only if /WR signal is delayed more than T_WHQX (Data Hold After /WR). For Atmel 8051 it is about t_clk-15ns. For example, with OSC=12MHz, the problem may appear if /WR is delayed with custom circuit longer than for ~68ns. As your schematic has /WR connected to /WR of RAM directly so do not worry. The situation goes worse if you use high-speed 8051 from Atmel. For example, the same time for AT89C51RD2 clocked with 60MHz, is only 1.5ns (!!!)

From other side, such "feature" may be used for debug purposes. Really, with some additional external hardware it is possible to catch current PCL during MOVX writes to external data memory. And so it is possible to know from which code address it was MOVX access.

Can you please let me know if this is being recorded in any errata sheets - and the work around suggested for the same. (links or files)

It is not need with workaround if your hardware is designed good (/WR is not long delayed). If by some reason your schematic goes over this limit then you just need to delay data bus as well (for example, with ALS245 etc).
As about Errata - no they do not indicate it as a hardware bug. Some datasheets just indicate it at Figure "Internal Clock Signals" at part "Write Cycle". For example, Datasheet of AT89C51RD2 at page 126.