Next I added checks whereever the software tried to let the SCL line go high I polled the SCL input to ensure that the SCL was actually high before stepping forward.<p>

Sorry for dragging up old topics this week, but I would like to 2nd the above to bit-banging protocols (be it I2C, PS2 or other). It seems with some hardware and/or some devices the target chip is not pulling (or perhaps releasing is a better word) the clock or data lines as fast as the new micros are able to turn around and look at the input state of a pin that it was just driving. I find it is often necessary to either provide for some means of waiting on the signal to rise or putting in some NOPs to give the bus more time to assume the high state.

GB